Petrohunter17

I am learning and practicing Verilog HDL. I wanted to design a 16 bit parallel in series out shift register. Module verilogshiftregistertestPISO( din, clk, load, dout ); output reg dout; i. N-bit Register with Asynchronous Reset Verilog - 4 Shift Register Example // 8-bit register can be cleared, loaded, shifted left / R etain sv lu f oc rg d module shiftReg (CLK, clr, shift, ld, Din, SI, Dout); input CLK; input clr; // clear register input shift; // shift input ld; // load register from Din input 7:0 Din; // Data input for load.

• 4 Bit Shift Register Verilog

Serial in serial out

// File : Design of Serial In -
Serial Out Shift Register using d_flip
flop.v
module siso ( din ,clk ,reset ,dout );
output dout ;
input din ;
input clk ;
input reset ;
wire [2:0]s;
d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(s[0]));
d_flip_flop u1 (.din(s[0]),
.clk(clk),
.reset(reset),
.dout(s[1]));
d_flip_flop u2 (.din(s[1]),
.clk(clk),
.reset(reset),
.dout(s[2]));
d_flip_flop u3 (.din(s[2]),
.clk(clk),
.reset(reset),
.dout(dout));
endmodule
// -------------- D flip flop design -
-----------------------
//------------------------------
--------------------------------
---------------
//
// Title : d_flip_flop
// Design : upload_design1
// Author : Naresh Singh Dobal
// Company : nsd
//
//------------------------------
--------------------------------
---------------
//
// File : d_flip_flop.v
module d_flip_flop ( din ,clk ,reset
,dout );
output dout ;
reg dout;
input din ;
input clk ;
input reset ;
always @ (posedge clk)
begin
if (reset)
dout <= 1;
else
dout <= din;
end
endmodule

Serial in parallel out

// File : Serial IN Parallel OUT
Shift Register using Behavior
Modeling Style.v
module SIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
wire [3:0] dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [3:0]s;
always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end
assign dout = s;
endmodule

Parallel in parallel out

// File : parallel IN - Parallel
OUT Shift Register using Behavior
Modeling Style.v
module PIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= din;
end
endmodule

Parallel in serial out

4 Bit Shift Register Verilog

// File : Parallel IN - Serial OUT
Shift Register.v
module parallel_in_serial_out ( din
,clk ,reset ,load ,dout );
output dout ;
reg dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp <= 1;
else if (load)
temp <= din;
else begin
dout <= temp[3];
temp <= {temp[2:0],1'b0};
end
end
endmodule